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SC18IS600 Fiches technique(PDF) 5 Page - NXP Semiconductors

No de pièce SC18IS600
Description  SPI to IC-bus interface
Download  28 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC18IS600 Fiches technique(HTML) 5 Page - NXP Semiconductors

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SC18IS600_601_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
5 of 28
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.
Functional description
The SC18IS600/601 acts as a bridge between a SPI interface and an I2C-bus. It allows a
SPI master device to communicate with I2C-bus slave devices. The SPI interface supports
Mode 3 of the SPI specification and can operate up to 3 Mbit/s (SC18IS601).
6.1 Internal registers
The SC18IS600/601 provides internal registers for monitoring and control. These
registers are shown in Table 3. Register functions are more fully described in the following
paragraphs.
[1]
For SC18IS601, these bits are ‘Don’t care’.
[2]
For SC18IS601 GPIO3 is not used.
6.2 Register descriptions
6.2.1 Programmable IO port configuration register (IOConfig)
Pins GPIO0 to GPIO3 may be configured by software to one of four types. These are:
quasi-bidirectional, push-pull, open-drain, and input-only. Two configuration bits per pin,
located in the IOConfig register, select the IO type for each pin. Each pin has
Schmitt-triggered input that also has a glitch suppression circuit. IO4 and IO5 are
quasi-bidirectional pins and are not user-configurable. For SC18IS601, GPIO3 is
non-existent.
Table 4 shows the configurations for the programmable I/O pins. IOx.1 and IOx.0
correspond to GPIOx.
Table 3.
Internal registers summary
Register
address
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Default
value
0x00
IOConfig
IO3.1[1]
IO3.0[1]
IO2.1
IO2.0
IO1.1
IO1.0
IO0.1
IO0.0
R/W
0x00
0x01
IOState
0
0
GPIO5
GPIO4
GPIO3[2]
GPIO2
GPIO1
GPIO0
R/W
0x3F
0x02
I2CClock
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
R/W
0x19
0x03
I2CTO
TO6
TO5
TO4
TO3
TO2
TO1
TO0
TE
R/W
0xFE
0x04
I2CStat
1
1
1
1
I2CSTAT3 I2CSTAT2 I2CSTAT1 I2CSTAT0 R
0xF0
0x05
I2CAdr
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
X
R/W
0x00
Table 4.
Pin configurations
IOx.1
IOx.0
Pin configuration
0
0
quasi-bidirectional output configuration
0
1
input-only configuration
1
0
push-pull output configuration
1
1
open-drain output configuration


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