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AD8196-EVAL Fiches technique(PDF) 6 Page - Analog Devices |
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AD8196-EVAL Fiches technique(HTML) 6 Page - Analog Devices |
6 / 24 page AD8196 Preliminary Technical Data PrA | Page 6 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE AD8196 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO MEET THERMAL SPECIFICATIONS. Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Type1 Description 1, 10, 33, 42 AVCC Power Positive Analog Supply. 3.3 V nominal. 2 IN_A0 HS I High Speed Input Complement. 3 IP_A0 HS I High Speed Input. 4, 13, 30, 39, ePAD AVEE Power Negative Analog Supply. 0 V nominal. 5 IN_A1 HS I High Speed Input Complement. 6 IP_A1 HS I High Speed Input. 7, 36 VTTI Power Input Termination Supply. Nominally connected to AVCC. 8 IN_A2 HS I High Speed Input Complement. 9 IP_A2 HS I High Speed Input. 11 IN_A3 HS I High Speed Input Complement. 12 IP_A3 HS I High Speed Input. 14 I2C_ADDR Control I2C Address LSB. 15, 21 DVCC Power Positive Digital Power Supply. 3.3 V nominal. 16 ON0 HS O High Speed Output Complement. 17 OP0 HS O High Speed Output. 18, 24 VTTO Power Output Termination Supply. Nominally connected to AVCC. 19 ON1 HS O High Speed Output Complement. 20 OP1 HS O High Speed Output. 22 ON2 HS O High Speed Output Complement. 23 OP2 HS O High Speed Output. 25 ON3 HS O High Speed Output Complement. 26 OP3 HS O High Speed Output. 27 AA RESETEE EA Control Configuration Registers Reset. This pin is normally pulled up to DVCC. 28 I2C_SCL Control I2C Clock. 29 I2C_SDA Control I2C Data. |
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