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MU9C8148 Fiches technique(PDF) 2 Page - MUSIC Semiconductors

No de pièce MU9C8148
Description  SRT Interface
Download  24 Pages
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Fabricant  MUSIC [MUSIC Semiconductors]
Site Internet  http://www.alldatasheet.com/
Logo MUSIC - MUSIC Semiconductors

MU9C8148 Fiches technique(HTML) 2 Page - MUSIC Semiconductors

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Rev. 5.5 Draft
web
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MU9C8148
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NC
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A4
A3
A2
A1
A0
/INT
/FULL,/EMPTY
/INTEL
/RESET
/EC
/CM
/FI
/MI
/E
/W
GND
VCC
GND
D11
D12
D13
D14
D15
/HBRDY
/HBEN
/HBDIR
/RQ
/RQI
XFAIL,/FLUSH
XMATCH
/RDY
RXD
RXC
VCC
NC
NC
GND
MU9C8148
80-pin TQFP
PINOUT DIAGRAMS
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VCC
GND
ALE, SRNW
/CS
/RS, /LDS
/WS, /UDS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
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MU9C8148
68-pin PLCC
LANCAM Interface:
DQ15–DQ0
(Data Bus, Input/Output, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8148 and the LANCAM. The direction and
nature of the information that flows between the devices is
determined by the states of /CM and /W.
/E
(Chip Enable, Output, Three-state TTL)
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
/W
(Write Enable, Output, Three-state TTL)
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
/CM (Data/Command Select, Output, Three-state
TTL)
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
/EC (Enable Comparison, Output, Three-state TTL)
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
/MI
(Match Flag, Input, TTL)
The LANCAM /MF pin takes the MU9C8148's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8148's routines.
/FI
(Full Flag, Input, TTL)
The /FI input will be driven LOW by the LANCAM /FF output pin
if all the LANCAM memory locations have valid contents. The
status of the /FI pin can be read by the Host processor from the
MU9C8148's Control register.
Transceiver Interface:
RXD
(Receive Data, Input, TTL)
The RXD pin monitors the data received by the TMS38053/4
from the Token Ring. RXD is clocked on the rising edge of
RXC.
PIN DESCRIPTIONS
(/X indicates an active LOW function)


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