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ADV7391BCPZ-REEL Fiches technique(PDF) 6 Page - Analog Devices

No de pièce ADV7391BCPZ-REEL
Description  Low Power, Chip Scale 10-Bit SD/HD Video Encoder
Download  96 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADV7391BCPZ-REEL Fiches technique(HTML) 6 Page - Analog Devices

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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 6 of 96
DIGITAL INPUT/OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Input Leakage Current, IIN
VIN = VDD_IO
±10
μA
Input Capacitance, CIN
4
pF
Output High Voltage, VOH
ISOURCE = 400 μA
2.4
V
Output Low Voltage, VOL
ISINK = 3.2 mA
0.4
V
Three-State Leakage Current
VIN = 0.4 V, 2.4 V
±1
μA
Three-State Output Capacitance
4
pF
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
Conditions
Min
Typ
Max
Unit
MPU PORT, I2C MODE1
SCL Frequency
0
400
kHz
SCL High Pulse Width, t1
0.6
μs
SCL Low Pulse Width, t2
1.3
μs
Hold Time (Start Condition), t3
0.6
μs
Setup Time (Start Condition), t4
0.6
μs
Data Setup Time, t5
100
ns
SDA, SCL Rise Time, t6
300
ns
SDA, SCL Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
See Figure 15
0.6
μs
MPU PORT, SPI MODE1
SCLK Frequency
0
10
MHz
SPI_SS to SCLK Setup Time, t1
20
ns
SCLK High Pulse Width, t2
50
ns
SCLK Low Pulse Width, t3
50
ns
Data Access Time after SCLK Falling Edge, t4
35
ns
Data Setup Time prior to SCLK Rising Edge, t5
20
ns
Data Hold Time after SCLK Rising Edge, t6
0
ns
SPI_SS to SCLK Hold Time, t7
0
ns
SPI_SS to MISO High Impedance, t8
See Figure 16
40
ns
1 Guaranteed by characterization.


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