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AD1988BJCPZ Fiches technique(PDF) 8 Page - Analog Devices |
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AD1988BJCPZ Fiches technique(HTML) 8 Page - Analog Devices |
8 / 20 page AD1988A/AD1988B Rev. 0 | Page 8 of 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 DVCORE GPIO_0/VOLUME DVI/O DVSS SDATA_OUT BIT_CLK DVSS SDATA_IN DVDD SYNC RESET PCBEEP PORT-D_L SENSE_B/SRC_A MIC_BIAS_FILT MIC_BIAS/EAPD-D MIC_BIAS-E MIC_BIAS-F MIC_BIAS/EAPD-C MIC_BIAS-B VREF_FILT AVSS AVDD 35 PORT-D_R 36 34 33 32 31 30 29 28 27 26 25 AD1988A/AD1988B TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 2. LFCSP_VQ Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 35 PORT-D_L 34 SENSE_B/SRC_A 33 MIC_BIAS_FILT 30 MIC_BIAS-F 31 MIC_BIAS-E 32 MIC_BIAS/EAPD-D 36 PORT-D_R 29 MIC_BIAS/EAPD-C 28 MIC_BIAS-B 27 VREF_FILT 25 AVDD 26 AVSS 2 GPIO_0/VOLUME 3 DVI/O 4 DVSS 7 DVSS 6 BIT_CLK 5 SDATA_OUT 1 DVCORE 8 SDATA_IN 9 DVDD 10 SYNC 12 PCBEEP 11 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 AD1988A/AD1988B TOP VIEW (Not to Scale) RESET Figure 3. LFQP Pin Configuration Table 5. Pin Function Descriptions Mnemonic Pin Number I/O Description DVCORE 1 O Filter Connection for Internal Core Voltage Regulator. This pin must be connected to filter capacitors: 10 μF, 1.0 μF, and 0.1 μF connected in parallel between Pin 1 and DVSS (Pin 4 and Pin 7). GPIO_0/VOLUME 2 I/O General-Purpose Input/Output Pin (Digital I/O). Digital signal used to control external circuitry. Volume Control. When enabled, it can be used as an external volume control DVIO 3 I Link Digital I/O Voltage Reference. 3.3 V (±10%). DVSS 4, 7 I Digital Supply Return (Ground). SDATA_OUT 5 I Link Serial Data Output (Digital Interface). AD1988 input stream. Clocked on both edges of the BIT_CLK. BIT_CLK 6 O Link Bit Clock (Digital Interface). 24.000 MHz serial data clock. SDATA_IN 8 I/O Link Serial Data Input (Digital Interface). AD1988 output stream. Clocked only on one edge of BIT_CLK. DVDD 9 I Digital Supply Voltage 3.3 V ± 10%. This is regulated down to 1.9 V on Pin 1 to supply the internal digital core internal to the AD1988. SYNC 10 I Link Frame Sync (Digital Interface). 48 kHz frame sync plus SDI stream IDs. RESET 11 I Link Reset (Digital Interface). AD1988 master hardware reset. PCBEEP 12 I Monaural Input from System for PCBEEP. Line level input. SENSE_A/SRC_B 13 I/O Jack Sense A to Jack Sense D Input/Sense B Drive. PORT-E_L, PORT-E_R 14, 15 I/O Left and Right Rear Panel Stereo Mic In/C/LFE (Analog Input/Output). Input: line level input, supports microphones with MIC_BIAS and boost amplifiers. Output: line level output. PORT-F_L, PORT-F_R 16, 17 I/O Left and Right Rear Panel Stereo Mic In/Surround Rear (Analog Input/Output). Input: line level input, supports microphones with MIC_BIAS and boost amplifiers. Output: line level output only. CD_L, CD_R 18, 20 I CD Audio Left Channel, CD Audio Right Channel. CD_GND 19 I CD Audio Analog Ground Reference (for Analog CD Input). Line level input only. PORT-B_L, PORT-B_R 21, 22 I/O Front Panel Stereo Mic In/Front Panel Headphones. Analog input/output. Input: line level input, supports microphones with MIC Bias and boost amplifiers. Output: line level output, capable of driving headphone load and power. |
Numéro de pièce similaire - AD1988BJCPZ |
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Description similaire - AD1988BJCPZ |
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