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FM3104-S Fiches technique(PDF) 15 Page - List of Unclassifed Manufacturers

No de pièce FM3104-S
Description  Integrated Processor Companion with Memory
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Fabricant  ETC1 [List of Unclassifed Manufacturers]
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FM3104-S Fiches technique(HTML) 15 Page - List of Unclassifed Manufacturers

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FM3104/16/64/256
Rev 0.2
May 2003
Page 15 of 22
Following the MSB is the LSB (lower byte) which
contains the remaining eight address bits. The
address is latched internally. Each access causes the
latched address to be incremented automatically. The
current address is the value that is held in the latch,
either a newly written value or the address following
the last access. The current address will be held as
long as VDD > VTP or until a new value is written.
Accesses to the clock do not affect the current
memory address. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
Acknowledge, the FM31xxx increments the internal
address. This allows the next sequential byte to be
accessed with no additional addressing externally.
After the last address is reached, the address latch
will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Addressing Overview – RTC & Companion
The RTC and Processor Companion operate in a
similar manner to the memory, except that it uses
only one byte of address. Addresses 00h to 18h
correspond to special function registers. Attempting
to load addresses above 18h is an illegal condition;
the FM31xxx will return a NACK and abort the 2-
wire transaction.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM31xxx begins. For a read, the FM31xxx will
place 8 data bits on the bus then wait for an ACK
from the master. If the ACK occurs, the FM31xxx
will transfer the next byte. If the ACK is not sent, the
FM31xxx will end the read operation. For a write
operation, the FM31xxx will accept 8 data bits from
the master then send an Acknowledge. All data
transfer occurs MSB (most significant bit) first.
Memory Write Operation
All memory writes begin with a Slave Address, then
a memory address. The bus master indicates a write
operation by setting the slave address LSB to a 0.
After addressing, the bus master sends each byte of
data to the memory and the memory generates an
Acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
to 0000h. Internally, the actual memory write occurs
after the 8th data bit is transferred. It will be complete
before the Acknowledge is sent. Therefore, if the
user desires to abort a write without altering the
memory contents, this should be done using a Start
or Stop condition prior to the 8th data bit. The figures
below illustrate a single- and multiple-writes to
memory.
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM31xxx
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Figure 11. Single Byte Memory Write
S
A
Slave Address
0
Address MSB
A
Data Byte
A
P
By Master
By FM31xxx
Start
Address & Data
Stop
Acknowledge
Address LSB
A
Data Byte
A
Figure 12. Multiple Byte Memory Write


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