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AD6654 Fiches technique(PDF) 8 Page - Analog Devices |
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AD6654 Fiches technique(HTML) 8 Page - Analog Devices |
8 / 88 page AD6654 Rev. 0 | Page 8 of 88 ELECTRICAL CHARACTERISTICS AVDD = 5.0 V, DRVDD = 3.3 V, VDDCORE = 1.8 V, VDDIO = 3.3 V, maximum rated sample rate, differential input, unless otherwise noted. Table 6. Parameter (Conditions) Temp Test Level Min Typ Max Unit LOGIC INPUTS (NOT 5 V TOLERANT) Logic Compatibility Full IV 3.3 V CMOS Logic 1 Voltage Full IV 2.0 3.6 V Logic 0 Voltage Full IV −0.3 +0.8 V Logic 1 Current Full IV 1 10 µA Logic 0 Current Full IV 1 10 µA Logic 1 Current (Inputs With Pull-Down) Full IV Logic 0 Current (Inputs With Pull-Up) Full IV Input Capacitance 25°C V 4 pF LOGIC OUTPUTS Logic Compatibility Full IV 3.3 V CMOS Logic 1 Voltage (IOH = 0.25 mA) Full IV 2.4 VDDIO − 0.2 V Logic 0 Voltage (IOL = 0.25 mA) Full IV 0.2 0.4 V SUPPLY CURRENTS WCDMA (92.16 MSPS) EXAMPLE1 IAVDD 25°C V 275 mA IDRVDD 25°C V 32 mA IVDD 25°C V 460 mA IVDDIO 25°C V 60 mA CDMA2000 (92.16 MSPS) EXAMPLE1 IAVDD 25°C V 275 mA IDRVDD 25°C V 32 mA IVDD 25°C V 435 mA IVDDIO 25°C V 25 mA TDS-CDMA (76.8 MSPS) EXAMPLE1, 2 IAVDD 25°C V 275 mA IDRVDD 25°C V 32 mA IVDD 25°C V 250 mA IVDDIO 25°C V 15 mA TOTAL POWER DISSIPATION WCDMA (92.16 MSPS)1 25°C V 2.5 W CDMA2000 (92.16 MSPS)1 25°C V 2.3 W TDS-CDMA (76.8 MSPS)1, 2 25°C V 2.0 W 1 ADC input port, all six DDC channels, and the relevant signal processing blocks are active. 2 PLL is turned off for power savings. |
Numéro de pièce similaire - AD6654 |
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Description similaire - AD6654 |
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