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STK16C88-3
March 2006
4
Document Control # ML0019 rev 0.2
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)
Note i:
If W is low when E goes low, the outputs remain in the high-impedance state.
Note j:
E or W must be
≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
SRAM WRITE CYCLE #2: E Controlledj
NO.
SYMBOLS
PARAMETER
STK16C88-3-35
UNITS
#1
#2
Alt.
MIN
MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
35
ns
13
tWLWH
tWLEH
tWP
Write Pulse Width
25
ns
14
tELWH
tELEH
tCW
Chip Enable to End of Write
25
ns
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
12
ns
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
ns
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
25
ns
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
ns
19
tWHAX
tEHAX
tWR
Address Hold after End of Write
0
ns
20
tWLQZ
h, i
tWZ
Write Enable to Output Disable
13
ns
21
tWHQX
tOW
Output Active after End of Write
5
ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA OUT
E
ADDRESS
12
tAVAV
W
DATA IN
13
tWLEH
DATA VALID
HIGH IMPEDANCE
14
tELEH
18
tAVEL
17
tAVEH
15
tDVEH
19
tEHAX
16
tEHDX
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