No. 7253-9/15

LC723481W/2W/3W

Continued from preceding page.

Pin No.

Pin

I/O

Function

I/O circuit

Continued on next page.

System reset input.

In CPU operating mode or halt mode, applications must apply a low level for at least

one full machine cycle to reset the system and restart execution with the PC set to

location 0. This pin is connected in parallel with the internal power on reset circuit.

54

BRES

I

Tuning voltage generation circuit outputs.

These pins include a n-ch transistor, and a tuning voltage can be generated by

connecting external coil, diode, and capacitor components.

49

TU

O

N-channel open-drain

FM VCO (local oscillator) input.

This pin is selected with the PLL instruction CW1.

57

FMIN

I

CMOS amplifier input

AM VCO (local oscillator) input.

This pin and the bandwidth are selected with the PLL instruction CW1.

The input must be capacitor coupled.

Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

58

AMIN

I

CMOS amplifier input

CW1 b1, b0

Bandwidth

1

0

2 to 40 MHz (SW)

1

1

0.5 to 10 MHz (MW, LW)

Special-purpose universal counter input port

• To measure a frequency, set up HCTR frequency measurement mode and the

measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the count with

a UCC instruction.

55

HCTR

I

CMOS amplifier input

UCS b3 b2

Input pin

Measurement

mode

0

0

HCTR

Frequency

measurement

0

1

—

—

1

0

—

—

The CNTEND flag is set when the count completes. Since the input circuit functions

as an AC amplifier in this mode, the input must be capacitance coupled.

This pin goes to the input disabled state in backup mode, halt mode, PLL stop mode,

and after a reset.

UCS b1 b0

Measurement time

0

0

1 ms

0

1

4 ms

1

0

8 ms

1

1

32 ms

The input must be capacitor coupled.

Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

CW1 b1, b0

Bandwidth

0

0

10 to 250 MHz