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LM3207 Datasheet(Fiches technique) 18 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numéro de pièce LM3207
Description  650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers with Integrated Vref LDO
Télécharger  19 Pages
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Fabricant  NSC [National Semiconductor (TI)]
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Logo NSC - National Semiconductor (TI)

LM3207 Datasheet(HTML) 18 Page - National Semiconductor (TI)

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Application Information (Continued)
Minimize C1, PV
and PGND loop. These traces
should be as wide and short as possible. This is most
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
Above layout patterns should be placed on the compo-
nent side of the PCB to minimize parasitic inductance
and resistance due to via-holes. It may be a good idea
that the SW to L1 path is routed between C2(+) and
C2(-) land patterns. If vias are used in these large cur-
rent paths, multiple via-holes should be used if possible.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as pos-
SGND should not connect directly to PGND. Connecting
these pins under the device should be avoided. (If pos-
sible, connect SGND to the common port of C1(-), C2(-)
and PGND.)
FB line should be protected from noise. It is a good idea
to use an inner GND layer (if available) as a shield.
The LDO Cap C7 (C
LDO) should be placed as close to
the PA as possible and as far away from the switcher to
suppress high frequency switch noises.
Note: The evaluation board shown in Figure 5 for the LM3207 was designed
with these considerations, and it shows good performance. However
some aspects have not been optimized because of limitations due to
evaluation-specific requirements. Please refer questions to a National
FIGURE 5. Evaluation Board Layout

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