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ADL5500 Datasheet(Fiches technique) 16 Page - Analog Devices

Numéro de pièce ADL5500
Description  100 MHz to 6 GHz TruPwr Detector
Télécharger  24 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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ADL5500 Datasheet(HTML) 16 Page - Analog Devices

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ADL5500
Rev. A | Page 16 of 24
INPUT COUPLING USING A SERIES RESISTOR
Figure 36 shows a technique for coupling the input signal into
the ADL5500 that can be applicable where the input signal is
much larger than the input range of the ADL5500. A series
resistor combines with the input impedance of the ADL5500 to
attenuate the input signal. Because this series resistor forms a
divider with the frequency dependent input impedance, the
apparent gain changes greatly with frequency. However, this
method has the advantage of very little power being tapped off
in RF power transmission applications. If the resistor is large
compared to the transmission line’s impedance, the VSWR of
the system is relatively unaffected.
ADL5500
RFIN
RFIN
RSERIES
Figure 36. Attenuating the Input Signal
MULTIPLE RF INPUTS
Figure 37 shows a technique for combining multiple RF input
signals to the ADL5500. Some applications can share a single
detector for multiple bands. Three 16.5 Ω resistors in a T-network
combine the three 50 Ω terminations (including the ADL5500).
The broadband resistive combiner ensures each port of the
T-network sees a 50 Ω termination. Because there is only 6 dB
of isolation from one port of the combiner to the other ports,
only one band should be active at a time.
ADL5500
RFIN
BAND 1
50
Ω
BAND 2
DIRECTIONAL
COUPLER
16.5
Ω
50
Ω
16.5
Ω
16.5
Ω
DIRECTIONAL
COUPLER
Figure 37. Combining Multiple RF Input Signals
SELECTING THE OUTPUT LOW-PASS FILTER
NETWORK
The ADL5500’s internal filter capacitor provides averaging in
the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA
or CDMA2000, can produce ac-residual levels on the ADL5500
dc output. To reduce the effects of these low frequency
components in the waveforms, some additional filtering is
required.
The output of the ADL5500 can be filtered by placing a
capacitor between VRMS (Pin 1) and ground. The combination
of the on-chip 1 kΩ output series resistance and the external
shunt capacitor forms a low-pass filter to reduce the residual ac.
Table 4 shows the effect of several capacitor values for various
communications standards with high peak-to-average ratios
along with the residual ripple at the output, in peak-to-peak and
rms volts. Note that large load capacitances increase the turn-on
and pulse response times (see Figure 29 and Figure 30).
Table 4. Waveform and Output Filter Effects on Residual AC
Output
Residual AC
Waveform
CFILT
V dc
mV p-p
mV rms
64QAM
0.01 μF
0.5
7.0
1.4
(7.4 dB CF)
1.0
7.4
1.5
2.0
7.6
1.6
0.1 μF
0.5
6.7
1.4
1.0
7.2
1.5
2.0
7.4
1.5
W-CDMA RL
0.01 μF
0.5
10
1.7
(3.4 dB CF)
1.0
16
2.4
2.0
45
5.6
0.1 μF
0.5
7
1.5
1.0
9
1.6
2.0
14
2.3
CDMA2000 UL
0.01 μF
0.5
46
6
(6.7 dB CF)
1.0
85
13
2.0
191
27
0.1 μF
0.5
17
3
1.0
31
5
2.0
68
9
POWER CONSUMPTION AND POWER-ON/-OFF
RESPONSE
The quiescent current consumption of the ADL5500 varies with
the size of the input signal from approximately 1 mA for no
signal up to 6 mA at an input level of 0.7 V rms (10 dBm, re
50 Ω). If the input is driven beyond this point, the supply
current increases sharply (as shown in Figure 6). There is little
variation in quiescent current with power supply voltage.
The ADL5500 can be disabled by simply removing the power to
the device. Figure 32 shows a plot of the output response to the
supply being turned on (that is, VPOS is pulsed) with an output
shunt capacitor of 0.01 μF. Again, the turn-on time is influenced
strongly by the size of the output shunt capacitor.
To improve the falling edge of the supply gating response and
the pulse response, a resistor can be placed in parallel with the
output shunt capacitor. The added resistance helps discharge
the capacitor. Although this method reduces the power-off
time, the added load resistor also attenuates the output (see the
Output Drive Capability and Buffering section).


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