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TPS54550 Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce TPS54550
Description  4.5-V TO 20-V INPUT, 6-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET (SWIFT)
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

TPS54550 Fiches technique(HTML) 8 Page - Texas Instruments

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DETAILED DESCRIPTION
Undervoltage Lockout (UVLO)
Slow Start Enable (SSENA) and Internal Slow
T
SS_INTERNAL(ms)
1.15k
ƒ
s(kHz)
(3)
5
µA
Disabled
Enabled
CSS
320 k
125 k
R1
R2
Input Voltage Supply
1 k
Extending Slow Start Time
R1
VIN(start)
1 kp
1.24 V
) 1kp
(1)
VIN(stop)
(R1 ) 1 kp)
1.02 V
1 kp
(2)
TPS54550
SLVS623A – MARCH 2006 – REVISED APRIL 2006
Start
The undervoltage lockout (UVLO) system has an
internal voltage divider from VIN to AGND. The
Once the SSENA pin voltage exceeds 0.5 V, the
defaults for the start/stop values are labeled VIN and
TPS54550 starts operation. The TPS54550 has an
given in Table 1. The internal UVLO threshold can be
internal digital slow start that ramps the reference
overridden by placing an external resistor divider from
voltage to its final value in 1150 switching cycles. The
VIN to ground. The internal divider values are
internal slow start time (10% - 90%) is approximated
approximately 320 k
Ω for the high side resistor and
by the following expression:
125 k
Ω for the low side resistor. The divider ratio (and
therefore the default start/stop values) is quite
accurate, but the absolute values of the internal
resistors may vary as much as 15%. If high accuracy
Once the TPS54550 device is in normal regulation,
is required for an externally adjusted UVLO threshold,
the SSENA pin is high. If the SSENA pin is pulled
select lower value external resistors to set the UVLO
below the stop threshold of 0.5 V, switching stops
threshold. Using a 1-k
Ω resistor for the low side
and the internal slow start resets. If an application
resistor R2 (see Figure 1) is recommended. Under no
requires the TPS54550 to be disabled, use open
circumstances should the UVLO pin be connected
drain or open collector output logic to interface to the
directly to VIN.
SSENA pin (see Figure 2). The SSENA pin has an
internal pullup current source. Do not use external
Table 1. Start/Stop Voltage Threshold
pullup resistors.
START VOLTAGE
STOP VOLTAGE
THRESHOLD
THRESHOLD
VIN (Default)
4.49
3.69
UVLO
1.24
1.02
Figure 2. Interfacing to the SSENA Pin
Figure 1. Circuit Using External UVLO Function
The equations for selecting the UVLO resistors are:
In applications that use large values of output
capacitance there may be a need to extend the slow
start time to prevent the startup current from tripping
the current limit. The current limit circuit is designed
to disable the high side MOSFET and reset the
internal voltage reference for a short amount of time
For applications which require an undervoltage lock
when the high side MOSFET current exceeds the
out (UVLO) threshold greater than 4.49 V, external
current limit threshold. If the output capacitance and
resistors may be implemented, see Figure 1, to adjust
load current cause the startup current to exceed the
the
start
voltage
threshold.
For
example,
an
current limit threshold, the power supply output will
application
needing
an
UVLO
start
voltage
of
not reach the desired output voltage. To extend the
approximately 7.8 V using the equation (1), R1 is
slow start time and to reduce the startup current, an
calculated to the nearest standard resistor value of
external capacitor can be added to the SSENA pin.
5.36 k
Ω. Using Equation 2, the input voltage stop
The slow start capacitance is calculated using the
threshold is calculated as 6.48 V.
following equation:
CSS(µF) = 5.55x10
-3 T
ss(ms)
8
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