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AD7946 Fiches technique(PDF) 5 Page - Analog Devices

No de pièce AD7946
Description  16-Bit, /-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD7946 Fiches technique(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
AD7693
Rev. PrB | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
0.5
1.6
μs
Acquisition Time
tACQ
400
ns
Time Between Conversions
tCYC
2.0
μs
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
17
ns
VIO Above 3 V
18
ns
VIO Above 2.7 V
19
ns
VIO Above 2.3 V
20
ns
SCK Low Time
tSCKL
7
ns
SCK High Time
tSCKH
7
ns
SCK Falling Edge to Data Remains Valid
tHSDO
4
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
14
ns
VIO Above 3 V
15
ns
VIO Above 2.7 V
16
ns
VIO Above 2.3 V
17
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 4.5 V
15
ns
VIO Above 2.7 V
18
ns
VIO Above 2.3 V
22
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
25
ns
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
tSSDICNV
15
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
10
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
3
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
4
ns
SDI High to SDO High (Chain Mode with BUSY Indicator)
tDSDOSDI
VIO Above 4.5 V
15
ns
VIO Above 2.3 V
26
ns
1 See Figure 3 and Figure 4 for load conditions.


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