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87LPC764 Fiches technique(PDF) 45 Page - NXP Semiconductors |
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87LPC764 Fiches technique(HTML) 45 Page - NXP Semiconductors |
45 / 56 page Philips Semiconductors Preliminary data 87LPC764 Low power, low price, low pin count (20 pin) microcontroller with 4 kbyte OTP 2001 Oct 26 42 Additional Features The AUXR1 register contains several special purpose control bits that relate to several chip features. AUXR1 is described in Figure 35. Software Reset The SRST bit in AUXR1 allows software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at program address 0000. Care should be taken when writing to AUXR1 to avoid accidental software resets. Dual Data Pointers The dual Data Pointer (DPTR) adds to the ways in which the processor can specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled. Specific instructions affected by the Data Pointer selection are: • INC DPTR Increments the Data Pointer by 1. • JMP @A+DPTR Jump indirect relative to DPTR value. • MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant. • MOVC A, @A+DPTR Move code byte relative to DPTR to the accumulator. • MOVX A, @DPTR Move data byte the accumulator to data memory relative to DPTR. • MOVX @DPTR, A Move data byte from data memory relative to DPTR to the accumulator. Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the 87LPC764 since the part does not have an external data bus. However, they may be used to access EPROM configuration information (see EPROM Characteristics section). Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. BIT SYMBOL FUNCTION AUXR1.7 KBF Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt function goes low. Must be cleared by software. AUXR1.6 BOD Brown Out Disable. When set, turns off brownout detection and saves power. See Power Monitoring Functions section for details. AUXR1.5 BOI Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows the brownout detect function to be used as an interrupt. See the Power Monitoring Functions section for details. AUXR1.4 LPEP Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can only be cleared by power-on or brownout reset. See the Power Reduction Modes section for details. AUXR1.3 SRST Software Reset. When set by software, resets the 87LPC764 as if a hardware reset occurred. AUXR1.2 — This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without interfering with other bits in the register. AUXR1.1 — Reserved for future use. Should not be set to 1 by user programs. AUXR1.0 DPS Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details. DPS SU01184 — 0 SRST LPEP BOI BOD KBF 0 1 2 3 4 5 6 7 AUXR1 Reset Value: 00h Not Bit Addressable Address: A2h Figure 35. AUXR1 Register |
Numéro de pièce similaire - 87LPC764 |
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Description similaire - 87LPC764 |
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