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74LVT273 Fiches technique(PDF) 3 Page - NXP Semiconductors |
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74LVT273 Fiches technique(HTML) 3 Page - NXP Semiconductors |
3 / 11 page Philips Semiconductors Product specification 74LVT273 3.3V Octal D flip-flop 1998 Feb 19 3 LOGIC SYMBOL (IEEE/IEC) 11 3 2 4 5 7 6 8 9 C1 13 12 14 15 17 16 18 19 1 R 1D SV00019 FUNCTION TABLE INPUTS OUTPUTS OPERATING MR CP Dn Q0 – Q7 OPERATING MODE L X X L Reset (clear) H ↑ h H Load “1” H ↑ l L Load “0” H L X Q0 Retain state H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition Q0 = Output as it was PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 11 CP Clock pulse input (active rising edge) 3, 4, 7, 8, 13, 14, 17, 18 D0 – D7 Data inputs 2, 5, 6, 9, 12, 15, 16, 19 Q0 – Q7 Data outputs 1 MR Master Reset input (active-Low) 10 GND Ground (0V) 20 VCC Positive supply voltage LOGIC DIAGRAM CP Q RD D 3 D0 Q0 CP Q RD D 4 D1 CP Q RD D 7 D2 CP Q RD D 8 D3 CP Q RD D 13 D4 CP Q RD D 14 D5 CP Q RD D 17 D6 CP Q RD D 18 D7 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 11 1 CP MR SV00020 |
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