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MC14549BCL Fiches technique(PDF) 6 Page - Motorola, Inc |
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MC14549BCL Fiches technique(HTML) 6 Page - Motorola, Inc |
6 / 9 page MOTOROLA CMOS LOGIC DATA MC14549B MC14559B 6 TYPICAL APPLICATIONS Externally Controlled 6–Bit ADC (Figure 2) Several features are shown in this application: • Shortening of the register to six bits by feeding the seventh output bit into the FF input. • Continuous conversion, if a continuous signal is applied to SC. • Externally controlled updating (the start pulse must be shorter than the conversion cycle). • The EOC output indicating that the parallel data are valid and that the serial output is complete. Continuously Cycling 8–Bit ADC (Figure 3) This ADC is running continuously because the EOC signal is fed back to the SC input, immediately initiating a new cycle on the next clock pulse. Continuously Cycling 12–Bit ADC (Figure 4) Because each successive approximation register (SAR) has a capability of handling only an eight–bit word, two must be cascaded to make an ADC with more than eight bits. When it is necessary to cascade two SAR’s, the second SAR must have a stable resettable state to remain in while awaiting a subsequent start signal. However, the first stage must not have a stable resettable state while recycling, be- cause during switch–on or due to outside influences, the first stage has entered a reset state, the entire ADC will remain in a stable non–functional condition. This 12–bit ADC is continuously recycling. The serial as well as the parallel outputs are updated every thirteenth clock pulse. The EOC pulse indicates the completion of Figure 2. Externally Controlled 6–Bit ADC TO DAC SC C Sout Q7 Q6 Q5 MC14559B Q4 Q3 Q2 Q1 Q0 EOC FF Figure 3. Continuously Cycling 8–Bit ADC TO DAC SC C Sout Q7 Q6 Q5 MC14559B Q4 Q3 Q2 Q1 Q0 EOC FF |
Numéro de pièce similaire - MC14549BCL |
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Description similaire - MC14549BCL |
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