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74LVT125DB Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74LVT125DB Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 10 page 9397 750 14703 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 05 — 10 February 2005 2 of 15 Philips Semiconductors 74LVT125 3.3 V quad buffer; 3-state 4. Ordering information 5. Functional diagram Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVT125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVT125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVT125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVT125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 leads terminals; body 2.5 × 3 × 0.85 mm SOT762-1 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram mna228 1A 1Y 2 1 3 1OE 2A 2Y 5 4 6 2OE 3A 3Y 9 10 8 3OE 4A 4Y 12 13 11 4OE mna229 1 EN1 1 3 2 4 6 5 10 8 9 13 11 12 mna227 nOE nA nY |
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