74LVC2245AD datasheet(2/17 Pages) PHILIPS

No de pièce	74LVC2245AD

Description	Octal transceiver with direction pin; 30 ohm series termination resistors; 5 V input/output tolerant; 3-state

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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2003 Nov 17

2

Philips Semiconductors

Product speciﬁcation

Octal transceiver with direction pin, 30

Ω series

termination resistors; 5 V tolerant input/output; 3-state

74LVC2245A

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Inputs accept voltages up to 5.5 V

• Integrated 30 Ω termination resistors

• Complies with JEDEC standard no. 8-1A

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC2245A is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. In

3-state operation, outputs can handle 5 V. These features

allow the use of these devices as translators in a mixed

3.3 and 5 V environment.

The 74LVC2245A is an octal transceiver featuring

non-inverting 3-state bus compatible outputs in both send

and receive directions.

The 74LVC2245A features an output enable (OE) input for

easy cascading and a send/receive (DIR) input for

direction control. OE controls the outputs so that the buses

are effectively isolated.

The 74LVC2245A is designed with 30

Ω series termination

resistors in both HIGH and LOW output stages to reduce

line noise.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

propagation delay An to Bn, Bn to An

CL = 50 pF; VCC = 3.3 V

3.6

ns

CI

input capacitance

4.0

pF

CPD

power dissipation capacitance per buffer

VCC = 3.3 V; notes 1 and 2

13

pF

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