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74LVC109 Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74LVC109 Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger 2 1998 Apr 28 853–1947 19308 FEATURES • Wide supply voltage range of 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output capability: standard • I CC category: flip-flops DESCRIPTION The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LVC109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ CL = 50 pF; VCC = 3.3 V 4.0 4.5 4.5 ns fmax Maximum clock frequency 250 MHz CI Input capacitance 5.0 pF CPD Power dissipation capacitance per flip-flop VI = GND to VCC1 27 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 16-Pin Plastic SO –40 °C to +85°C 74LVC109 D 74LVC109 D SOT109-1 16-Pin Plastic SSOP Type II –40 °C to +85°C 74LVC109 DB 74LVC109 DB SOT338-1 16-Pin Plastic TSSOP Type I –40 °C to +85°C 74LVC109 PW 74LVC109PW DH SOT403-1 PIN CONFIGURATION SV00517 1R D 1K 1CP 1S D V CC 2R D 2J 2K 2CP 2S D 2Q 2Q 1J 1Q 1Q GND 14 13 12 11 10 9 8 1 2 3 4 5 6 7 16 15 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 15 1RD, 2RD Asynchronous reset input (active LOW) 2, 14, 3, 13 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2 4, 12 1CP, 2CP Clock input (LOW-to-HIGH, edge-triggered) 5, 11 1SD, 2SD Asynchronous set inputs (active LOW) 6, 10 1Q, 2Q True flip-flop outputs 7, 9 1Q, 2Q Complement flip-flop outputs 8 GND Ground (O V) 16 VCC Positive supply voltage |
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Description similaire - 74LVC109 |
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