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7403 Fiches technique(PDF) 15 Page - NXP Semiconductors |
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7403 Fiches technique(HTML) 15 Page - NXP Semiconductors |
15 / 28 page September 1993 15 Philips Semiconductors Product specification 4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403 Notes to Fig.9 1. DOR HIGH; no data transfer in progress, valid data is present at output stage 2. SO set HIGH; results in DOR going LOW 3. DOR goes LOW; output stage “busy” 4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input stage 5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay 6. Repeat process to unload the 3rd through to the 64th word from FIFO 7. DOR remains LOW; FIFO is empty. Fig.9 Waveforms showing the SO input to DOR output propagation delay. The SO pulse widths and maximum pulse frequency. handbook, full pagewidth MGA661 VM (1) SO INPUT Qn OUTPUT 1/f max W t DOR OUTPUT t PHL t PLH VM (1) VM (1) 1st SO pulse 2nd SO pulse 64th SO pulse 1st word 2nd word 64th word 7 3 15 6 4 2 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
Numéro de pièce similaire - 7403 |
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Description similaire - 7403 |
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