December 1990

2

Philips Semiconductors

Product specification

Dual 4-bit binary ripple counter

74HC/HCT393

FEATURES

• Two 4-bit binary counters with individual clocks

• Divide-by any binary module up to 28 in one package

• Two master resets to clear each 4-bit counter

individually

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT393 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT393 are 4-bit binary ripple counters with

separate clocks (1CP and 2 CP) and master reset (1MR

and 2MR) inputs to each counter. The operation of each

half of the “393” is the same as the “93” except no external

clock connections are required.

The counters are triggered by a HIGH-to-LOW transition of

the clock inputs. The counter outputs are internally

connected to provide clock inputs to succeeding stages.

The outputs of the ripple counter do not change

synchronously and should not be used for high-speed

address decoding.

The master resets are active-HIGH asynchronous inputs

to each 4-bit counter identified by the “1” and “2” in the pin

description.

A HIGH level on the nMR input overrides the clock and

sets the outputs LOW.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

12

20

ns

56

ns

11

15

ns

maximum clock frequency

99

53

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per counter

notes 1 and 2

23

25

pF