74HC273PW datasheet(2/8 Pages) PHILIPS

No de pièce	74HC273PW

Description	Octal D-type flip-flop with reset; positive-edge trigger

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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September 1993

2

Philips Semiconductors

Product speciﬁcation

Octal D-type ﬂip-ﬂop with reset;

positive-edge trigger

74HC/HCT273

FEATURES

• Ideal buffer for MOS microprocessor or memory

• Common clock and master reset

• Eight positive edge-triggered D-type flip-flops

• See “377” for clock enable version

• See “373” for transparent latch version

• See “374” for 3-state version

• Output capability; standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT273 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT273 have eight edge-triggered, D-type

flip-flops with individual D inputs and Q outputs. The

common clock (CP) and master reset (MR) inputs load and

reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the

LOW-to-HIGH clock transition, is transferred to the

corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or

data inputs by a LOW voltage level on the MR input.

The device is useful for applications where the true output

only is required and the clock and master reset are

common to all storage elements.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5 V

CP to Qn

15

ns

MR to Qn

15

20

ns

fmax

maximum clock frequency

66

36

MHz

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per flip-flop

notes 1 and 2

20

23

pF

Numéro de pièce similaire - 74HC273PW

Fabricant	No de pièce	Fiches technique	Description
Nexperia B.V. All right...	74HC273PW	279Kb / 17P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 7 - 6 September 2021
NXP Semiconductors	74HC273PW-Q100	147Kb / 19P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 1-19 June 2013
Nexperia B.V. All right...	74HC273PW-Q100	277Kb / 18P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 2 - 3 September 2020

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Description similaire - 74HC273PW

Fabricant	No de pièce	Fiches technique	Description
NXP Semiconductors	74HC273-Q100	147Kb / 19P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 1-19 June 2013
Nexperia B.V. All right...	74LVC273-Q100	715Kb / 16P	Octal D-type flip-flop with reset; positive-edge trigger
NXP Semiconductors	74AHC273	92Kb / 20P	Octal D-type flip-flop with reset; positive-edge trigger 1999 Sep 01
	74AHC273	111Kb / 18P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 03-13 May 2008
	74LV273	117Kb / 12P	Octal D-type flip-flop with reset; positive-edge trigger 1998 May 29
Nexperia B.V. All right...	74LVC273	259Kb / 14P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 8 - 31 August 2021
Nexperia B.V. All right...	74HCT273	279Kb / 17P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 7 - 6 September 2021
NXP Semiconductors	74LVC273	95Kb / 10P	Octal D-type flip-flop with reset; positive-edge trigger 1998 May 20
NXP Semiconductors	74HC273D-653	153Kb / 21P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 4-10 June 2013
Nexperia B.V. All right...	74AHC273-Q100	814Kb / 19P	Octal D-type flip-flop with reset; positive-edge trigger
Nexperia B.V. All right...	74HC273-Q100	277Kb / 18P	Octal D-type flip-flop with reset; positive-edge trigger Rev. 2 - 3 September 2020

More results

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