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74HCT20D Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74HCT20D Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 6 page December 1990 2 Philips Semiconductors Product specification Dual 4-input NAND gate 74HC/HCT20 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT20 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT20 provide the 4-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf =6ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC HCT tPHL/ tPLH propagation delay nA, nB, nC, nD to nY CL = 15 pF; VCC = 5 V 8 13 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package notes 1 and 2 22 17 pF |
Numéro de pièce similaire - 74HCT20D |
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Description similaire - 74HCT20D |
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