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74HC161D Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74HC161D Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 12 page December 1990 11 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74HC/HCT161 AC WAVEFORMS Fig.8 Waveforms showing the clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the input (CET) to output (TC) propagation delays and output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
Numéro de pièce similaire - 74HC161D |
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Description similaire - 74HC161D |
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