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74HC58D Fiches technique(PDF) 2 Page - NXP Semiconductors |
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74HC58D Fiches technique(HTML) 2 Page - NXP Semiconductors |
2 / 5 page December 1990 2 Philips Semiconductors Product specification Dual AND-OR gate 74HC58 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V 1n to 1Y 11 ns 2n to 2Y 9 ns CI input capacitance 3.5 pF CPD power dissipation capacitance per gate notes 1 and 2 18 pF |
Numéro de pièce similaire - 74HC58D |
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Description similaire - 74HC58D |
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