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74ALVCH16501DGG Datasheet(Fiches technique) 2 Page - NXP Semiconductors

Numéro de pièce 74ALVCH16501DGG
Description  18-bit universal bus transceiver 3-State
Télécharger  13 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
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Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
2
1998 Sep 29
853–2091 20106
FEATURES
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
All inputs have bushold circuitry
Output drive capability 50Ω transmission lines @ 85°C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates
in the transparent mode when LEAB is High. When LEAB is Low, the
A data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is High, the outputs are
active. When OEAB is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA
and CPBA. The output enables are complimentary (OEAB is active
High, and OEBA is active Low).
To ensure the high impedance state during power up or power
down, OEBA should be tied to VCC through a pullup resistor and
OEAB should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf = 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An, Bn to Bn, An
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
2.8
3.0
ns
CI/O
Input/output capacitance
8.0
pF
CI
Input capacitance
4.0
pF
CPD
Power dissipation capacitance per
VI = GND to VCC1
Outputs enabled
21
pF
CPD
latch
VI = GND to VCC1
Outputs disabled
3
F
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
DWG NUMBER
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVCH16501 DGG
SOT364-1




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