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74AHC74D Fiches technique(PDF) 11 Page - NXP Semiconductors |
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74AHC74D Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 20 page 1999 Sep 23 11 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 AC WAVEFORMS Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth MNA422 th tsu th tPHL tPHL tW tPLH tPLH tsu 1/fmax VM (1) VM (1) VM (1) VM (1) VI GND VI GND nCP INPUT nD INPUT VOH VOL nQ OUTPUT VOH VOL nQ OUTPUT FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(1) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC |
Numéro de pièce similaire - 74AHC74D |
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Description similaire - 74AHC74D |
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