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SI9124 Fiches technique(PDF) 8 Page - Vishay Siliconix |
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SI9124 Fiches technique(HTML) 8 Page - Vishay Siliconix |
8 / 16 page Si9124 Vishay Siliconix New Product www.vishay.com 8 Document Number: 72099 S-03638—Rev. B, 20-Mar-03 DETAILED FUNCTIONAL BLOCK DIAGRAM Figure 5. + - 132 k W EP + - - + - + VREG 9.1 V VCC VIN Pre-Regulator VUVLO 8.6 V Reference Voltage 3.3 V Voltage Feedforward OSC 160 _C Temp Protection VSD VUV VUVLO Logic Clock OTP VREF VINDET - + ROSC Oscillator Clock 60 k W VREF/2 PWM Generator - + - + VUV VSD VREF 550 mV Logic OUTA VCC2 PGND2 Primary A Driver OUTB SEC_SYNC PGND Primary B Driver Secondary Synchronous Driver GND Current Control Gain 100 mV CS2 CS1 VCC VCC Blanking SS Enable VCC 20 mA 80 mA SS Control SS VREF 9.1 V DETAILED OPERATION Start-Up A detailed Functional Block Diagram is shown in Figure 5 with additional detail of the pre-regulator shown in Figure 6. The pre-regulator circuit acts as a linear regulator to provide VCC directly from the VINEXT supply until the VCC supply voltage between 10 V to 13.2 V can be sustained from an auxiliary winding from the secondary of the power inductor. When VINEXT rises above 0 V (see Figure 6), the internal pre-regulator begins charging the external capacitor on VCC. The charging current is limited to typically 40 mA by the internal DMOS device. When Vcc exceeds the UVLO voltage of 8.8 V, a soft-start cycle of the controller is initiated to provide power to the secondary. Once switching commences, the internal gate drivers for the primary side switching transistors and the drive current into the secondary synchronization driver draw additional current from the VCC capacitor and pre-regulator. |
Numéro de pièce similaire - SI9124 |
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