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GS8662D36GE-167 Fiches technique(PDF) 8 Page - GSI Technology |
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GS8662D36GE-167 Fiches technique(HTML) 8 Page - GSI Technology |
8 / 29 page Preliminary GS8662D08/09/18/36E-333/300/250/200/167 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01a 2/2006 8/29 © 2005, GSI Technology SigmaQuad-II B4 SRAM DDR Write The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and finally by the next rising edge of K. and by the rising edge of the K that follows. SigmaQuad-II B4 Double Data Rate SRAM Write First Write A NOP Read B Write C Read D Write E NOP A B C D E A A+1 A+2 A+3 C C+1 C+2 C+3 E E+1 E+ A A+1 A+2 A+3 C C+1 C+2 C+3 E E+1 E+ B B+1 B+2 B+3 D D+1 D+2 K K Address R W BWx D C C Q CQ CQ |
Numéro de pièce similaire - GS8662D36GE-167 |
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Description similaire - GS8662D36GE-167 |
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