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GS8321E18E-166V Fiches technique(PDF) 5 Page - GSI Technology |
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GS8321E18E-166V Fiches technique(HTML) 5 Page - GSI Technology |
5 / 31 page GS8321E18/32/36E-xxxV 165-Bump BGA Pin Description Symbol Type Description A0, A1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I Clock Input Signal; active high BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E1 I Chip Enable; active low E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active l0w ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL — Must Connect Low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply GS8321E18/32/36E-xxxV Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.04 6/2006 5/31 © 2003, GSI Technology |
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