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GS8640E18T-200V Fiches technique(PDF) 1 Page - GSI Technology

No de pièce GS8640E18T-200V
Description  4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

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Preliminary
GS8640E18/32/36T-xxxV
4M x 18, 2M x 32, 2M x 36
72Mb Sync Burst SRAMs
250 MHz–167 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.01 6/2006
1/23
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline
operation
• Dual Cycle Deselect (DCD) operation
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS8640E18/32/36T-xxxV is a 75,497,472-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS8640E18/32/36T-xxxV is a DCD (Dual Cycle
Deselect) pipelined synchronous SRAM. SCD (Single Cycle
Deselect) versions are also available. DCD SRAMs pipeline
disable commands to the same degree as read commands. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge
of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8640E18/32/36T-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible.
Separate output power (VDDQ) pins are used to decouple
output noise from the internal circuits and are 1.8 V or 2.5 V
compatible.
Parameter Synopsis
-250
-200
-167
Unit
Pipeline
3-1-1-1
tKQ
tCycle
3.0
4.0
3.0
5.0
3.5
6.0
ns
ns
Curr (x18)
Curr (x32/x36)
340
410
290
350
260
305
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
6.5
6.5
7.5
7.5
8.0
8.0
ns
ns
Curr (x18)
Curr (x32/x36)
245
280
220
250
210
240
mA
mA


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