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GS8161FZ36BD-6.5I Fiches technique(PDF) 5 Page - GSI Technology

No de pièce GS8161FZ36BD-6.5I
Description  18Mb Flow Through Synchronous NBT SRAM
Download  28 Pages
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8161FZ36BD-6.5I Fiches technique(HTML) 5 Page - GSI Technology

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GS8161FZ18/32/36BD 165-Bump BGA Pin Description
Symbol
Type
Description
A0, A1
I
Address field LSBs and Address Counter Preset Inputs
A
I
Address Inputs
DQA
DQB
DQC
DQD
I/O
Data Input and Output pins
BA, BB, BC, BD
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC
No Connect
CK
I
Clock Input Signal; active high
CKE
I
Clock Input Buffer Enable; active low
W
I
Write Enable; active low
E1
I
Chip Enable; active low
E3
I
Chip Enable; active low
E2
I
Chip Enable; active high
G
I
Output Enable; active low
ADV
I
Burst address counter advance enable; active high
ZZ
I
Sleep mode control; active high
LBO
I
Linear Burst Order mode; active low
TMS
I
Scan Test Mode Select
TDI
I
Scan Test Data In
TDO
O
Scan Test Data Out
TCK
I
Scan Test Clock
MCH
Must Connect High
VDD
I
Core power supply
VSS
I
I/O and Core Ground
VDDQ
I
Output driver power supply
GS8161FZ18/32/36BD
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 6/2006
5/28
© 2006, GSI Technology


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