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GS8160F32BGT-6.5I Fiches technique(PDF) 7 Page - GSI Technology

No de pièce GS8160F32BGT-6.5I
Description  1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
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Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8160F32BGT-6.5I Fiches technique(HTML) 7 Page - GSI Technology

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Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
GS8160F18/32/36BT-5.5/6.5/7.5
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 9/2005
7/22
© 2004, GSI Technology
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in
the above tables.
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Burst Counter Sequences
BPR 1999.05.18


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