Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

GS8160F36BGT-6.5 Fiches technique(PDF) 1 Page - GSI Technology

No de pièce GS8160F36BGT-6.5
Description  1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
Download  22 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  GSI [GSI Technology]
Site Internet  http://www.gsitechnology.com
Logo GSI - GSI Technology

GS8160F36BGT-6.5 Fiches technique(HTML) 1 Page - GSI Technology

  GS8160F36BGT-6.5 Datasheet HTML 1Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 2Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 3Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 4Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 5Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 6Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 7Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 8Page - GSI Technology GS8160F36BGT-6.5 Datasheet HTML 9Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 22 page
background image
GS8160F18/32/36BT-5.5/6.5/7.5
1M x 18, 512K x 32, 512K x 36
18Mb Sync Burst SRAMs
5.5 ns–8.5 ns
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
100-Pin TQFP
Commercial Temp
Industrial Temp
Rev: 1.03 9/2005
1/22
© 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Flow Through mode operation; Pin 14 = No Connect
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
Applications
The GS8160F18/32/36BT is an 18,874,368-bit (16,777,216-bit
for x32 version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC standard for Burst RAMS calls for a FT mode pin
option on Pin 14. Board sites for flow through Burst RAMS
should be designed with VSS connected to the FT pin location
to ensure the broadest access to multiple vendor sources.
Boards designed with FT pin pads tied low may be stuffed with
GSI’s pipeline/flow through-configurable Burst RAMs or any
vendor’s flow through or configurable Burst SRAM. Boards
designed with the FT pin location tied high or floating must
employ a non-configurable flow through Burst RAM, like this
RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS8160F18/32/36BT operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-5.5
-6.5
-7.5
Unit
Flow Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
ns
ns
Curr (x18)
Curr (x32/x36)
225
255
200
220
185
205
mA
mA


Numéro de pièce similaire - GS8160F36BGT-6.5

FabricantNo de pièceFiches techniqueDescription
logo
GSI Technology
GS8160F36BGT-6.5IV GSI-GS8160F36BGT-6.5IV Datasheet
860Kb / 21P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160F36BGT-6.5V GSI-GS8160F36BGT-6.5V Datasheet
860Kb / 21P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
More results

Description similaire - GS8160F36BGT-6.5

FabricantNo de pièceFiches techniqueDescription
logo
GSI Technology
GS8160V18AT GSI-GS8160V18AT Datasheet
489Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018DGT-250I GSI-GS816018DGT-250I Datasheet
255Kb / 25P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BT GSI-GS816018BT Datasheet
925Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160F18T GSI-GS8160F18T Datasheet
544Kb / 22P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160E18BT-V GSI-GS8160E18BT-V Datasheet
926Kb / 23P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8160EV18AT GSI-GS8160EV18AT Datasheet
490Kb / 24P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS8161E18 GSI-GS8161E18 Datasheet
946Kb / 36P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018BT-V GSI-GS816018BT-V Datasheet
927Kb / 23P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816018 GSI-GS816018 Datasheet
810Kb / 28P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816036DGT-250IV GSI-GS816036DGT-250IV Datasheet
245Kb / 23P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
logo
List of Unclassifed Man...
GS816118 ETC1-GS816118 Datasheet
901Kb / 36P
   1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com