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GS841E18AI-133I Fiches technique(PDF) 7 Page - GSI Technology |
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GS841E18AI-133I Fiches technique(HTML) 7 Page - GSI Technology |
7 / 21 page GS841E18AT/B-180/166/150/130/100 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.03 4/2005 7/21 © 2001, GSI Technology Mode Pin Function LBO Function L Linear Burst H or NC Interleaved Burst FT Function L Flow Through H or NC Pipeline Power Down Control Note: There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. ZZ Function L or NC Active H Standby, IDD = ISB Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 Note: H = logic high, L = logic low, NC = no connect Byte Write Function Function GW BWE BW1 BW2 Read H H X X Read H L H H Write all bytes L X X X Write all bytes H L L L Write byte 1 H L L H Write byte 2 H L H L |
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Description similaire - GS841E18AI-133I |
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