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FW323061394 Fiches technique(PDF) 11 Page - Agere Systems

No de pièce FW323061394
Description  PCI PHY/Link Open Host Controller Interface
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FW323061394 Fiches technique(HTML) 11 Page - Agere Systems

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Agere Systems Inc.
11
Data Sheet, Rev. 1
FW323 06 1394a
December 2005
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description (continued)
Figure 4. Link Core Block Diagram
Link Core
The link core shown in Figure 4 consists of the following blocks:
Link Control State Machine: main link state machine that controls all other link core modules.
Transmit (TX): reads from the AT and IT FIFOs and forms 1394 packets for transmit.
Receive (RX): pipes incoming 1394 packet data to appropriate FIFO (if any).
Address Decoder: decodes the destination ID of an incoming 1394 packet to determine if an acknowledge is
needed.
CRC: calculates and checks CRC on outgoing and incoming packets.
Isochronous Control Timer: contains the logic for the 1394 cycle timer.
DataMUX: pipes 1394 data to and from various modules.
Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the
PCI core.
PHY-Link Interface: interfaces with the 1394 physical layer.
RX
TX
LINK CONTROL
STATE
MACHINE
CRC
DATAMUX
ISOCH
CONTROL
TIMER
ADDRESS
DECODER
INTERFACE
CONTROL
AR FIFO
AT FIFO
IR FIFO
IT FIFO
PHY - LINK
INTERFACE
PHYDATA
PHYCTL
PHYLREQ
PCI SLAVE


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