FW801BF datasheet(8/26 Pages) AGERE

No de pièce	FW801BF

Description	Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device

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8

Agere Systems Inc.

Data Sheet

January 2005

One-Cable Transceiver/Arbiter Device

FW801BF PHY 1394a-2000

Signal Information (continued)

Table 2. Signal Descriptions (continued)

Ball

Number

Signal*

Type

Name/Description

H4

ISON

I

Link Interface Isolation Disable Input (Active-Low). ISON controls the

operation of an internal pulse differentiating function used on the

PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.

When ISON is asserted low, the isolation barrier is implemented between

PHY and its LLC (as described in Annex J of IEEE 1394-1995).

ISON is normally tied high to disable isolation differentiation. Bus-keepers

are enabled when ISON is high (inactive) on CTLn, Dn, and LREQ. When

ISON is low (active), the bus-keepers are disabled. Please refer to

Agere’s application note, 1394 Isolation (AP05-014CMPR) for more infor-

mation.

G1

LPS

I

Link Power Status. LPS is connected to either the VDD supplying the

LLC or to a pulsed output that is active when the LLC is powered for the

purpose of monitoring the LLC power status. If LPS is inactive for more

than 1.2

µs and less than 25 µs, the PHY-link interface is reset. If LPS is

inactive for greater than 25

µs, the PHY will disable the PHY/link interface

to save power. FW801BF continues its repeater function.

A2

LREQ

I

Link Request. LREQ is an output from the LLC that requests the PHY to

perform some service. Bus-keeper circuitry is built into this terminal.

H3

PD

I

Powerdown. When asserted high, PD turns off all internal circuitry except

the bias-detect circuits that drive the CNA signal. Internal FW801BF logic

is kept in the reset state as long as PD is asserted. The PD terminal is

provided for backward compatibility. It is recommended that the FW801BF

be allowed to manage its own power consumption using suspend/resume

in conjunction with LPS. C_LKON features are defined in the IEEE 1394a-

2000 specification.

B4

VDDPLL

—

Power for PLL Circuit. VDDPLL supplies power to the PLL circuitry

portion of the device.

B3

VSSPLL

—

Ground for PLL Circuit. VSSPLL is tied to a low-impedance ground

plane.

A7

R[0]

I

Current Setting Resistor. An internal reference voltage is applied to a

resistor connected between R0 and R1 to set the operating current and

the cable driver output current. A low temperature-coefficient resistor

(TCR) with a value of 2.49 k

Ω ± 1% should be used to meet the IEEE

1394-1995 standard requirements for output voltage limits.

B6

R[1]

B2

RESETN

I

Reset (Active-Low). When RESETN is asserted low (active), a 1394 bus

reset condition is set on the active cable port and the FW801BF is reset to

the reset start state. To guarantee that the PHY will reset, this ball must be

held low for at least 2 ms. An internal pull-up resistor connected to VDD is

provided so that only an external delay capacitor (0.1

µF) and resistor

(510 k

Ω) in parallel, are required to connect this ball to ground. This

circuitry will ensure that the capacitor will be discharged when PHY power

is removed. The input is a standard logic buffer and can also be driven by

an open-drain logic output buffer. Do not leave this ball unconnected.

E7

SE

I

Test Mode Control. SE is used during Agere’s manufacturing test and

should be tied to VSS for normal operation.

* Active-low signals are indicated by “N” at the end of signal names, within this document.

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