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LM27213MTD Fiches technique(PDF) 6 Page - National Semiconductor (TI) |
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LM27213MTD Fiches technique(HTML) 6 Page - National Semiconductor (TI) |
6 / 22 page Electrical Characteristics Specifications with standard typeface are for T J = 25˚C, and those in bold face type apply over a junction temperature range of -5˚C to +110˚C. Unless otherwise specified, VDD = 5V, SGND = DGND = PGND = SRCK = 0V, unless otherwise stated. (Note 5) (Continued) Symbol Parameter Conditions Min Typ Max Units V dac DAC Accuracy Measured at VREF pin % DAC codes from 0.7V to 0.828V -1.3 1.3 DAC codes from 0.844V to 1.004V -1.1 1.1 DAC codes from 1.020V to 1.196V -0.9 0.9 DAC codes from 1.212V to 1.356V -1 1 DAC codes from 1.372V to 1.500V -1.1 1.1 DAC codes from 1.516V to 1.708V -1.3 1.3 V1R7 V1R7 Accuracy 17k Ω from V1R7 to GND -1.674 1.708 1.742 V VSTP Offset VSTP = 1.398V, Measured at VREF pin -5 5 mV VBOOT Offset VBOOT = 1.00V, Measured at VREF pin -5 5 mV VSLP Offset VSLP = 0.748V, Measured at VREF pin -5 5 mV I VREF VREF Driving Capability source 1.3 mA sink 12.6 mA I VDAC VDAC Driving Capability source 1.3 mA sink 13.4 mA I V1R7 V1R7 Driving Capability source 90 549 µA Error Comparator I BEC Error Comparator Input Bias Current (Sourcing) CMP = 1.436V. 12 21 33 µA V OSEC Error Comparator Input Offset Voltage CMPREF = 1.436V. -3 3 mV I HYST Hysteresis Current (bi-directional) R hys = 17kW 38 50 68 µA R hys = 170kW 5 µA Current Limit I BCLC Current Limit Comparator Input Bias Current 9 21 35 µA V OSCLC Current Limit Comparator Input Offset Voltage ILIMREF = 1.436V. -2 2 mV Current Limit Setting Current R hys = 17kW, ILIMREF < ILIMx 280 337 395 µA R hys = 17kW, ILIMREF > ILIMx 250 µA R hys = 170kW, ILIMREF < ILIMx 30 µA Time Delays t BOOT VBOOT Voltage Holdup Time From assertion of XPOK to assertion of CLK_EN#. 10 17 30 µs t CPU_PWRGD Power Good Mask For Initial VID Voltage Settling From assertion of CLK_EN# to assertion of PGOOD. 3 5 9 ms t MASK Power Good Mask For VID Changes 100 129 179 µs t dPG Power Good De-assertion Delay Upon Shutdown Delay From VR_ON de-assertion to PGOOD de-assertion 60 ns Over-voltage Protection V TRIP SENSE Voltage As A Percentage of VOVP VOVP = V1R7 109 125 139 % System DE_EN# LH DE_EN# Input Logic High 0.63 0.56 V DE_EN# LL DE_EN# Input Logic Low 0.47 0.315 V I DE_EN# DE_EN# Pin Leakage Current DE_EN# = 7.5V 6 100 µA V SDT Soft Shutdown Finish Threshold Low-side driver enabled after shutdown 0.3 V www.national.com 6 |
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