74V1G77 datasheet(1/10 Pages) STMICROELECTRONICS

No de pièce	74V1G77

Description	SINGLE D-TYPE LATCH

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April 2004

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HIGH SPEED: tPD = 4.4ns (TYP.) at VCC =5V

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LOW POWER DISSIPATION:

ICC =1µA(MAX.) at TA=25°C

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HIGH NOISE IMMUNITY:

VNIH =VNIL = 28% VCC (MIN.)

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POWER DOWN PROTECTION ON INPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|= IOL =8mA (MIN) at VCC =4.5V

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BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

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OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 5.5V

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V1G77 is an advanced high-speed CMOS

SINGLE

D-TYPE

LATCH

fabricated

with

sub-micron silicon gate and double-layer metal

wiring C2MOS technology. It is designed to

operate from 2V to 5.5V, making this device ideal

for portable applications.

The single D-Type latch is controlled by a Latch

Enable Input (LE).

While the LE input is held at a high level, the Q

output will follow the data input precisely. When

the LE input is taken low the Q output is latched

precisely at the logic level of D input data.

Power down protection is provided on inputs and

0 to 7V can be accepted on inputs with no regard

to the supply voltage. This device can be used to

interface 5V to 3V. It’s available in the commercial

and extended temperature range.

All inputs and output are equipped with protection

circuits against static discharge, giving them ESD

immunity and transient excess voltage.

74V1G77

SINGLE D-TYPE LATCH

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

T & R

SOT23-5L

74V1G77STR

SOT323-5L

74V1G77CTR

SOT323-5L

SOT23-5L

Numéro de pièce similaire - 74V1G77

Fabricant	No de pièce	Fiches technique	Description
STMicroelectronics	74V1G70	48Kb / 7P	SINGLE BUFFER October 1999
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	74V1G70CTR	108Kb / 9P	SINGLE BUFFER
	74V1G70S	48Kb / 7P	SINGLE BUFFER October 1999

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Description similaire - 74V1G77

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