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P87LPC779 Fiches technique(PDF) 23 Page - NXP Semiconductors

No de pièce P87LPC779
Description  CMOS single-chip 8-bit 80C51 microcontroller with 128-byte data RAM, 8 kB OTP
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P87LPC779 Fiches technique(HTML) 23 Page - NXP Semiconductors

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Philips Semiconductors
P87LPC779
CMOS single-chip 8-bit microcontroller
Product data
Rev. 02 — 03 May 2004
23 of 74
9397 750 13213
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.7.2
Reading I2CON
RDAT — The data from SDA is captured into ‘Receive DATa’ whenever a rising edge
occurs on SCL. RDAT is also available (with seven low-order zeros) in the I2DAT
register. The difference between reading it here and there is that reading I2DAT
clears DRDY, allowing the I2C-bus to proceed on to another bit. Typically, the first
seven bits of a received byte are read from I2DAT, while the 8th is read here. Then
I2DAT can be written to send the Acknowledge bit and clear DRDY.
ATN — ‘ATteNtion’ is ‘1’ when one or more of DRDY, ARL, STR, or STP is ‘1’. Thus,
ATN comprises a single bit that can be tested to release the I2C-bus service routine
from a ‘wait loop.’
DRDY — ‘Data ReaDY’ (and thus ATN) is set when a rising edge occurs on SCL,
except at idle slave. DRDY is cleared by writing CDR = 1, or by writing or reading the
I2DAT register. The following low period on SCL is stretched until the program
responds by clearing DRDY.
8.7.3
Checking ATN and DRDY
When a program detects ATN = ‘1’, it should next check DRDY. If DRDY = ‘1’, then if it
receives the last bit, it should capture the data from RDAT (in I2DAT or I2CON). Next,
if the next bit is to be sent, it should be written to I2DAT. One way or another, it should
clear DRDY and then return to monitoring ATN. Note that if any of ARL, STR, or STP
is set, clearing DRDY will not release SCL to HIGH, so that the I2C-bus will not go on
to the next bit. If a program detects ATN = ‘1’, and DRDY = ‘0’, it should go on to
examine ARL, STR, and STP.
ARL — ‘Arbitration Loss’ is ‘1’ when transmit Active was set, but this device lost
arbitration to another transmitter. Transmit Active is cleared when ARL is ‘1’. There
are four separate cases in which ARL is set:
1. If the program sent a ‘1’ or repeated start, but another device sent a ‘0’, or a stop,
so that SDA is ‘0’ at the rising edge of SCL. (If the other device sent a stop, the
setting of ARL will be followed shortly by STP being set.)
2. If the program sent a ‘1’, but another device sent a repeated start, and it drove
SDA LOW before SCL could be driven LOW. (This type of ARL is always
accompanied by STR = ‘1’.)
3. In master mode, if the program sent a repeated start, but another device sent a
‘1’, and it drove SCL LOW before this device could drive SDA LOW.
4. In master mode, if the program sent stop, but it could not be sent because
another device sent a ‘0’.
STR — ‘STaRt’ is set to a ‘1’ when an I2C-bus start condition is detected at a non-idle
slave or at a master. (STR is not set when an idle slave becomes active due to a start
bit; the slave has nothing useful to do until the rising edge of SCL sets DRDY.)
STP — ‘SToP’ is set to ‘1’ when an I2C-bus stop condition is detected at a non-idle
slave or at a master. (STP is not set for a stop condition at an idle slave.)
MASTER — ‘MASTER’ is ‘1’ if this device is currently a master on the I2C-bus.
MASTER is set when MASTRQ is ‘1’ and the bus is not busy (i.e., if a start bit hasn’t
been received since reset or a ‘Timer I’ time-out, or if a stop has been received since
the last start). MASTER is cleared when ARL is set, or after the software writes
MASTRQ = ‘0’ and then XSTP = ‘1’.


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