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P87LPC779 Fiches technique(PDF) 38 Page - NXP Semiconductors |
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P87LPC779 Fiches technique(HTML) 38 Page - NXP Semiconductors |
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38 / 74 page  Philips Semiconductors P87LPC779 CMOS single-chip 8-bit microcontroller Product data Rev. 02 — 03 May 2004 38 of 74 9397 750 13213 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. If the Brownout Detect function is not required in an application, it may be disabled, thus saving power. Brownout Detect is disabled by setting the control bit BOD in the AUXR1 register (AUXR1.6). 8.11.2 Power-on detection The Power-on Detect has a function similar to the Brownout Detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout Detect can work. When this feature is activated, the POF flag in the PCON register is set to indicate an initial power up condition. The POF flag will remain set until cleared by software. 8.12 Power reduction modes The P87LPC779 supports Idle and Power-down modes of power reduction. 8.12.1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or Reset may terminate Idle mode. Idle mode is entered by setting the IDL bit in the PCON register (see Tables 29 and 30). 8.12.2 Power-down mode The Power-down mode stops the oscillator in order to absolutely minimize power consumption. Power-down mode is entered by setting the PD bit in the PCON register (see Tables 29 and 30). The processor can be made to exit Power-down mode via Reset or one of the interrupt sources shown in Table 28. This will occur if the interrupt is enabled and its priority is higher than any interrupt currently in progress. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VRAM, therefore it is recommended to wake up the processor via Reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Since the Watchdog timer has a separate oscillator, it may reset the processor upon overflow if it is running during Power-down. Note that if the Brownout Detect reset is enabled, the processor will be put into reset as soon as VDD drops below the brownout voltage. If Brownout Detect is configured as an interrupt and is enabled, it will wake up the processor from Power-down mode when VDD drops below the brownout voltage. When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. Oscillator stability is determined by counting 1024 CPU clocks after start-up when one of the crystal oscillator configurations is used, or 256 clocks after start-up for the internal RC or external clock input configurations. |
Numéro de pièce similaire - P87LPC779 |
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Description similaire - P87LPC779 |
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