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DEVICE INFORMATION

VBST

LL

V5DRV

1

EN_PSV

TON

PGOOD

DRVH

DRVL

VFB

VOUT

14

13

12

11

10

9

2

3

4

5

6

V5FILT

TRIP

7

8

GND

PGND

TSSOP (PW) PACKAGE

(TOP VIEW)

TPS51117

SLVS631 – DECEMBER 2005

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

High-side NFET gate driver output. Source 5

Ω, sink 1.5 Ω LL-node referenced driver. Drive voltage

DRVH

13

O

corresponds to VBST to LL voltage.

Rectifying (low-side) NFET gate driver output. Source 5

Ω, sink 1.5 Ω PGND referenced driver. Drive voltage

DRVL

9

O

is V5DRV voltage.

Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and

EN_PSV

1

I

activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode).

GND

7

I

Signal ground pin.

LL

12

I/O

High-side NFET gate driver return. Also serves as anode of overcurrent comparator.

Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the

PGND

8

I/O

output discharge switch.

Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current

PGOOD

6

O

capability is 7.5 mA.

TON

2

I

On-time / frequency adjustment pin. Connect to LL with 100-k

Ω to 600-kΩ resistor.

Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both

TRIP

11

I

overcurrent and negative overcurrent limit.

Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An

VBST

14

I

internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if

forward drop is critical to drive the power NFET.

VFB

5

I

SMPS voltage feedback input. Connect the resistor divider here for adjustable output.

Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment,

VOUT

3

I

and input for the output discharge switch.

5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1

µF or

V5DRV

10

I

more between this pin and PGND to support instantaneous current for gate drivers.

5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17

V5FILT

4

I

300

Ω + 1 µF or 100 Ω + 4.7 µF at the pin input.

5