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T6L24 Datasheet(Fiches technique) 4 Page - Toshiba Semiconductor

Numéro de pièce T6L24
Description  TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC SOURCE DRIVER FOR TFT LCD PANELS
Télécharger  12 Pages
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

T6L24 Datasheet(HTML) 4 Page - Toshiba Semiconductor

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T6L24
2002-01-07
4
Pin Function
Pin Name
I/O
Function
DI/O
DO/I
I/O
Vertical shift data I/O pins
These pins are used to input and output shift data. These pins are switched between input and
output by setting the U/D pin as shown below:
U/D
DI/O
DO/I
H
Input
Output
L
Output
Input
When set for input
When MODE
= low
The data is latched into the internal logic synchronously with the rising edge of CPH. The data
is sampling in sequentially, starting at the rise of CPH after three clock period.
When MODE
= high
The data is latched into the internal logic synchronously with the rising edge of CPH. The data
is sampling in sequentially, starting at the next rise of CPH.
When set for output
When two or more T6L24s are cascaded, this pin outputs the data to be fed into the next stage.
U/D
I
Transfer direction select pin
This pin specifies the direction of sampling performed by the sample-and-hold circuit.
When MODE
= low
When U/D is high, data is sampled in the sequence
SA1
® SB1 ® SC1 ® SA2 ® SB2 ® × × × ® SC80
When U / D is low, the sequence is reversed to give
SC80
® SB80 ® SA80 ® SC79 ® × × × ® SA1
When MODE
= high
When U/D is high, data is sampled in the sequence
SA1, SB1, SC1
® SA2, SB2, SC2 ® × × × ® SA80, SB80, SC80
When U/D is low, the sequence is reversed to give
SC80, SB80, SA80
® SC79, SB79, SA79 ® × × × ® SC1, SB1, SA1
CPH
I
Shift clock input
This clock sequentially shift the signals necessary to sample the data that are output to the LCD
drive output pins (QA1 to QC80).
CX
I
Sample-and-hold switching pin.
This pin switches between two sample−and−hold circuits.
MODE
I
Sampling mode setting pin.
When MODE
= high
Simultaneously samples three video output signals corresponding to the LCD drive outputs.
When MODE
= low
Sequentially samples the video output signals corresponding to the LCD drive outputs.
VA
VB
VC
I
Analog signal input
These pins accept as their input the analog signals that are output to the LCD drive output pins.
C-COM
I
Sample and hold reference voltage input
This is the reference voltage for the sample-and-hold circuit.
Apply stable DC voltage to the pin.
QA1 to QA80
QB1 to QB80
QC1 to QC80
O
LCD drive output pins
These pins output one of the analog signal inputs (VA, VB and VC) after it has been sampled and
held by the sample-and-hold circuit.
DVDD
¾
Power supply for the device’s logic block
AVDD
¾
Power supply for the device’s high−voltage block
DVSS
¾
Digital GND for the device
AVSS
¾
Analog GND for the device
TST
¾
Test pin
Use the pin as required.


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