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SN74AUP1G02YZPR Fiches technique(PDF) 4 Page - Texas Instruments |
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SN74AUP1G02YZPR Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 13 page SN74AUP1G02 LOW POWER SINGLE 2INPUT POSITIVENOR GATE SCES568B − JUNE 2004 − REVISED JUNE 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 0.8 3.6 V VCC = 0.8 V VCC VIH High-level input voltage VCC = 1.1 V to 1.95 V 0.65 × VCC V VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.6 V VCC = 3 V to 3.6 V 2 VCC = 0.8 V 0 VIL Low-level input voltage VCC = 1.1 V to 1.95 V 0.35 × VCC V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V VCC = 3 V to 3.6 V 0.9 VI Input voltage 0 3.6 V VO Output voltage 0 VCC V VCC = 0.8 V −20 µA VCC = 1.1 V −1.1 IOH† High-level output current VCC = 1.4 V −1.7 IOH† High-level output current VCC = 1.65 −1.9 mA VCC = 2.3 V −3.1 mA VCC = 3 V −4 VCC = 0.8 V 20 µA VCC = 1.1 V 1.1 IOL† Low-level output current VCC = 1.4 V 1.7 IOL† Low-level output current VCC = 1.65 V 1.9 mA VCC = 2.3 V 3.1 mA VCC = 3 V 4 ∆t/∆v Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V TA Operating free-air temperature −40 85 °C † Defined by the signal-integrity requirements and design-goal priorities. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. |
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Description similaire - SN74AUP1G02YZPR |
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