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BD63731EFV Datasheet(Fiches technique) 14 Page - Rohm
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BD63731EFV Datasheet(HTML) 14 Page - Rohm
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© 2019 ROHM Co., Ltd. All rights reserved.
• 15 • 001
This series has a built in translator circuit and can drive stepping motor in CLK-IN mode.
The operation of the translator circuit in CLK-IN drive mode is described as below.
The translator circuit is initialized by power ON Reset function and the PS Pin.
1.1 Initializing operation when power supply is turned on
If power supply is turned on at PS=L (Use this sequence as a general rule)
When power supply is turned on, the power ON reset function is initialized and operates the IC,
but as long as it is PS=L, the motor output is the OPEN state. After power supply is turned on,
the motor output becomes ACTIVE state by changing PS=L to H, and the excitation is started at
the initial electrical angle.
But at the time of PS=L to H, it returns from the standby state to the normal state and there is a
delay of 40 μs (Max) until the motor output has become the ACTIVE state.
If power supply is turned on at PS=H
When power supply is turned on and the power ON reset function in IC operates, and be
initialized before the motor output becomes the ACTIVE state during EN=H, and the excitation is
started at the initial electrical angle.
1.2 Initializing operation during motor operating
Enter a reset signal to the PS pin to initialize the translator circuit during motor operation. (Refer to P.18) But
at the time of PS=L to H, it returns from the standby state to the normal state and there is a delay of 40
(Max) until the motor output has become the ACTIVE state, so within this delay interval there is no phase
advance operation even if CLK is inputted.
Control Input Timing
Shown below is the operation of the translator circuit at the rising edge of CLK signal. If you disobey this timing and
input, then there is the possibility that the translator circuit does not operate as expected. In addition, at the time of
PS=L to H, it returns from the standby state to the normal state and there is a delay of 40
μs (Max) until the motor
output has become the ACTIVE state, so within this delay interval there is no phase advance operation even if CLK is
A: PS minimum input pulse width
… 20 μs
B: PS rising edge to CLK rising edge input possible maximum delay time
… 40 μs
C: CLK minimum period
… 4 μs
D: CLK minimum input H pulse width
… 2 μs
E: CLK minimum input L pulse width
… 2 μs
F: MODE0, MODE1, MODE2, CW_CCW, ENABLE set-up time
… 1 μs
G: MODE0, MODE1, MODE2, CW_CCW, ENABLE hold time
… 1 μs
Reset is released
Motor output OPEN
Motor output ON
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