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ST16C32245TTR Fiches technique(PDF) 1 Page - STMicroelectronics |
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ST16C32245TTR Fiches technique(HTML) 1 Page - STMicroelectronics |
1 / 20 page 1/20 October 2004 s HIGH SPEED: tPD = 4.4ns (MAX.) at TA=85°C VCCA = 3.0V VCCB = 2.3V s LOW POWER DISSIPATION: ICCA = ICCB = 20µA(MAX.) at TA=85°C s SYMMETRICAL OUTPUT IMPEDANCE: |IOHA| = IOLA = 8mA MIN at VCCA = 3.0V VCCB = 1.65V or 2.3V |IOHB| = IOLB = 6mA MIN at VCCB = 1.65V VCCA = 3V) s BALANCED PROPAG. DELAYS: tPLH ≅ tPHL s POWER DOWN PROTECTION ON I/O s 26 ΩSERIESRESISTOR ON ASIDEOUTPUTS s OPERATING VOLTAGE RANGE: VCCA(OPR)=2.3V to 3.6V (1.2V Data Retent) VCCB(OPR)=1.65V to 2.7V (1.2V Data Retent) s FAST I2C LINES 1.8V/2.8V LEVEL TRANSLATOR: 400KHz GUARANTEED DATA RATE AT CL = 15pF s BUS HOLD PROVIDED ON DATA INPUT BOTH SIDE s LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) s ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The ST16C32245 is a dual supply low voltage CMOS 14-BIT BUS TRANSCEIVER fabricated with sub-micron silicon gate and five-layer metal wiring C2MOS technology. Designed for use as an interface between a 3.3V bus and a 2.5V or 1.8V bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/ 1.8V supply systems, it achieves high speed operation while maintaining the CMOS low power dissipation and it includes 2-bit I2C level translation. This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by nDIR inputs. The enable inputs nG can be used to disable the device so that the buses are effectively isolated. The A-port interfaces with the 3V bus, the B-port with the 2.5V and 1.8V bus. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. All floating bus terminals during High Z State don’t need external pull-up or pull-down resistor. ST16C32245 14 BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR, A SIDE SERIES RESISTOR, 2 BIT I2C LINES This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Table 1: Order Codes PACKAGE T & R TSSOP48 ST16C32245TTR TFBGA54 ST16C32245LBR µTFBGA42 ST16C32245TBR TSSOP µTFBGA TFBGA PRELIMINARY DATA Figure 1: Logic Diagram Rev. 1 |
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