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CDC950 Fiches technique(PDF) 9 Page - Texas Instruments |
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CDC950 Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 16 page CDC950 133MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS SCAS646B − FEBRUARY 2001 − REVISED OCTOBER 2003 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) CLK33 (Type 5) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage VDD = min to max, IOH = –1 mA VDD – 0.1 VOH High-level output voltage VDD = 3.135 V, IOH = −18 mA 2.4 V VOL Low-level output voltage VDD = min to max, IOL = 1 mA 0.1 V VOL Low-level output voltage VDD = 3.135 V, IOL = 12 mA 0.15 0.4 VDD = 3.135 V, VO = 1 V −33 IOH High-level output current VDD = 3.3 V, VO = 1.65 V −53 IOH High-level output current VDD = 3.465 V, VO = 3.135 V −16 −33 mA VDD = 3.135 V, VO = 1.95 V 30 mA IOL Low-level output current VDD = 3.3 V, VO = 1.65 V 51 IOL Low-level output current VDD = 3.465 V, VO = 0.4 V 21 38 CO Output capacitance VDD = 3.3 V, VO = VDD or GND 4.5 7.5 pF Zo Output impedance High state VO = 0.5 VDD, VO/IOH 12 35 55 Ω Zo Output impedance Low state VO = 0.5 VDD, VO/IOL 12 35 55 Ω † All typical values are measured at their respective nominal VDD values. switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT V(over) Overshoot† HCLK/HCLK 0.7-V VOH + 200 mV V(under) Undershoot† HCLK/HCLK 0.7-V amplitude VOL − 200 mV V(over) Overshoot† Other clocks, GND − 0.7 V V(under) Undershoot† Other clocks, CL = worst case VDD + 0.7 V tPZL Output enable time from low level SEL100/133 All outputs SEL100/133 ↑ Rref = 475 Ω 10 tPZH Output enable time to high level SEL100/133 All outputs SEL100/133 ↑ Rref = 475 Ω 10 ns tPHZ Output disable time from high level SEL100/133 All outputs SEL100/133 ↓ Rref = 475 Ω 10 ns tPLZ Output disable time from low level SEL100/133 All outputs SEL100/133 ↓ Rref = 475 Ω 10 ts Stabilization time‡ VDD All outputs After power up 0.1 ms ts Stabilization time‡ PWRDWN All outputs From PWRDWN ↑ 0.25 ms † These parameters are assured by design and lab characterization, not 100% production tested. ‡ Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at XIN. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time since VDD achieves its nominal operating level (3.3 V) or PWRDWN transition from a low to a high level (2 V) until the output frequency is stable and operating within specification. |
Numéro de pièce similaire - CDC950 |
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Description similaire - CDC950 |
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