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Moteur de recherche de fiches techniques de composants électroniques |
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M68HC11ERG Fiches technique(PDF) 52 Page - Motorola, Inc |
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M68HC11ERG Fiches technique(HTML) 52 Page - Motorola, Inc |
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52 / 60 page  M68HC11ERG/AD 52 M68HC11E Series Programming Reference Guide MOTOROLA Timer Interrupt Mask Register 1 (TMSK1) OC1I–OC4I — Output Compare x Interrupt Enable If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit. IC1I–IC3I — Input Capture x Interrupt Enable If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. Timer Interrupt Mask Register 2 (TMSK2) TOI — Timer Overflow Interrupt Enable 0 = TOF interrupts disabled 1 = Interrupt requested when TOF is set to 1 RTII — Real-Time Interrupt Enable 0 = RTIF interrupts disabled 1 = Interrupt requested when RTIF is set to 1 PAOVI — Pulse Accumulator Input Edge Interrupt Enable 0 = PAOVF interrupts disabled 1 = Interrupt requested when PAOVF is set to 1 PAII — Pulse Accumulator Input Edge Interrupt Enable 0 = PAIF interrupts disabled 1 = Interrupt requested when PAIF is set to 1 Bits [3:2] — Unimplemented Always reads 0 PR[1:0] — Timer Prescaler Select In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles after reset. Address: $1022 Bit 7 654321 Bit 0 Read: OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I Write: Reset: 00000000 Address: $1024 Bit 7 654321 Bit 0 Read: TOI RTII PAOVI PAII PR1 PR0 Write: Reset: 00000000 = Unimplemented PR1 PR0 Prescaler 00 ÷ 1 01 ÷ 4 10 ÷ 8 11 ÷ 16 |
Numéro de pièce similaire - M68HC11ERG |
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Description similaire - M68HC11ERG |
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