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GS8161E32D-150I Fiches technique(PDF) 10 Page - GSI Technology |
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GS8161E32D-150I Fiches technique(HTML) 10 Page - GSI Technology |
10 / 36 page GS8161E18(T/D)/GS816132(D)/GS816136(T/D) Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.13 11/2004 10/36 © 1999, GSI Technology Note: There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences BPR 1999.05.18 Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, IDD = ISB Single/Dual Cycle Deselect Control SCD L Dual Cycle Deselect H or NC Single Cycle Deselect FLXDrive Output Impedance Control ZQ L High Drive (Low Impedance) H or NC Low Drive (High Impedance) 9th Bit Enable PE L Activate DQPx I/Os (x18/x36 mode) H or NC Deactivate DQPx I/Os (x16/x32 mode) Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
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