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MC10EP57DTR2 Fiches technique(PDF) 2 Page - ON Semiconductor |
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MC10EP57DTR2 Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 10 page MC10EP57, MC100EP57 http://onsemi.com 2 Figure 1. 20−Lead Package (Top View) and Logic Diagram D1 D1 D2 D0 17 18 16 15 14 13 12 4 3 567 8 9 SEL0 11 10 VCC Q VCC VBB1 VBB2 VEE D0 19 20 2 1 VCC SEL1 D2 VCC D3 VEE D3 4:1 Q Table 1. PIN DESCRIPTION PIN D0−3*, D0−3* SEL0*, 1* ECL MUX Select Inputs FUNCTION ECL Diff. Data Inputs VBB1, VBB2 Q, Q ECL Data Outputs ECL Reference Output Voltage VCC VEE Negative Supply Positive Supply D0, D0 D1, D1 D2, D2 D3, D3 L L H H L H L H Table 2. FUNCTION TABLE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. * Pins will default LOW when left open. DATA OUT SEL1 SEL0 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k W Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 584 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. |
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